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1/23 september 2004 m68af127b 1mbit (128k x8), 5v asynchronous sram features summary supply voltage: 4.5 to 5.5v 128k x 8 bits sram with output enable equal cycle and access times: 55ns low standby current low v cc data retention: 2v tri-state common i/o low active and standby power figure 1. packages 32 1 so32 (mc) pdip32 (b) tsop32 (nk) 8 x 13.4mm tsop32 (n) 8 x 20mm
m68af127b 2/23 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. so connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. operating and ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10.chip enable or output enable controlled, read mode ac waveforms . . . . . . . . . . . . . 11 figure 11.chip enable controlled, standby mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. read and standby mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12.write enable controlled, write ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 13.chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 14.e1 controlled, low v cc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 15.e2 controlled, low v cc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. low v cc data retention characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16.so32 - 32 lead plastic small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. so32 - 32 lead plastic small outline, package mechanical data. . . . . . . . . . . . . . . . . . 17 figure 17.pdip32 - 32 pin plastic dip, 600 mils width, package outline . . . . . . . . . . . . . . . . . . . . 18 table 11. pdip32 - 32 pin plastic dip, 600 mils width, package mechanical data . . . . . . . . . . . . 18 figure 18.tsop32 - 32-lead thin small outline package, 8x13.4mm, package outline . . . . . . . . 19
3/23 m68af127b table 12. tsop32 - 32-lead thin small outline package, 8x13.4mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 19.tsop32 - 32 lead plastic thin small outline, 8x20mm, package outline . . . . . . . . . . . 20 table 13. tsop32 - 32 lead plastic thin small outline, 8x20mm, package mechanical data . . . 20 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
m68af127b 4/23 summary description the m68af127b is a 1mbit (1,048,576 bit) cmos sram, organized as 131,072 words by 8 bits. the device features fully static operation requiring no external clocks or timing strobes, with equal ad- dress access and cycle times. it requires a single 4.5 to 5.5v supply. this device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. the m68af127b is available in so32, pdip32, tsop32 (8x13.4mm) and tsop32 (8x20mm) packages. figure 2. logic diagram table 1. signal names ai05472b 17 a0-a16 w dq0-dq7 v cc m68af127b g v ss 8 e1 e2 a0-a16 address inputs dq0-dq7 data input/output e1 chip enable e2 chip enable g output enable w write enable v cc supply voltage v ss ground
5/23 m68af127b figure 3. so connections figure 4. dip connections figure 5. tsop connections dq5 dq6 dq7 dq0 v ss dq3 dq4 dq1 dq2 a12 a15 a14 a16 a6 nc g w a8 a10 a11 a9 a13 a5 a7 a2 a0 a3 a4 a1 ai07270b m68af127b 8 1 9 16 17 24 25 32 v cc e2 e1 ai07203b m68af127b 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq5 dq6 dq7 dq3 dq4 a15 g w a8 a10 a11 a9 a13 v cc e2 e1 dq0 v ss dq1 dq2 a12 a14 a16 a6 nc a5 a7 a2 a0 a3 a4 a1 a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 e2 a11 v ss dq5 dq2 dq3 dq4 dq6 a15 w a16 a12 nc v cc a14 ai05473d m68af127b 8 1 9 16 17 24 25 32 g e1 dq1 dq7
m68af127b 6/23 figure 6. block diagram ai05471 row decoder a7 a16 dq0 dq7 column decoder i/o circuits a0 a6 w g memory array e1 e2 ex
7/23 m68af127b operation the m68af127b has a chip enable power down feature which invokes an automatic standby mode whenever chip enable is de-asserted (e1 = high), or chip select is asserted (e2 = low). an output enable (g ) signal provides a high-speed, tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. opera- tional modes are determined by device control in- puts w and e1 as summarized in the operating modes table (table 2). read mode the m68af127b is in the read mode whenever write enable (w ) is high with output enable (g ) low, chip enable (e1 ) is asserted and chip select (e2) is de-asserted. this provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. valid data will be available at the eight output pins within t avqv after the last stable address, provid- ing g is low and e1 is low. if chip enable or out- put enable access times are not met, data access will be measured from the limiting parameter (t elqv or t glqv ) rather than the address. data out may be indeterminate at t elqx and t glqx , but data lines will always be valid at t avqv . write mode the m68af127b is in the write mode whenever the w and e1 pins are low and the e2 pin is high. either the chip enable input (e1 ) or the write en- able input (w ) must be de-asserted during ad- dress transitions for subsequent write cycles. write begins with the concurrence of e1 being ac- tive with w low. therefore, address setup time is referenced to write enable and chip enable as t avwl and t aveh , respectively, and is determined by the latter occurring edge. the write cycle can be terminated by the earlier rising edge of e1 , or w . if the output is enabled (e1 = low, e2 = high and g = low), then w will return the outputs to high im- pedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of op- eration. data input must be valid for t dvwh before the rising edge of write enable, or for t dveh before the rising edge of e1 , whichever occurs first, and remain valid for t whdx or t ehdx . table 2. operating modes note: x = v ih or v il . operation e1 e2 w g dq0-dq7 power read v il v ih v ih v ih hi-z active (i cc ) read v il v ih v ih v il data output active (i cc ) write v il v ih v il x data input active (i cc ) deselect v ih x x x hi-z standby (i sb ) deselect x v il x x hi-z standby (i sb )
m68af127b 8/23 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 3. absolute maximum ratings note: 1. one output at a time, not to exceed 1 second duration. 2. up to a maximum operating v cc of 6.0v only. symbol parameter value unit i o (1) output current 20 ma t a ambient operating temperature ?55 to 125 c t stg storage temperature ?65 to 150 c v cc supply voltage ?0.5 to 6.5 v v io (2) input or output voltage ?0.5 to v cc +0.5 v p d power dissipation 1 w
9/23 m68af127b dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. operating and ac measurement conditions figure 7. ac measurement i/o waveform figure 8. ac measurement load circuit parameter m68af127b v cc supply voltage 4.5 to 5.5v ambient operating temperature range 1 0 to 70c range 6 ?40 to 85c load capacitance (c l ) 100pf output circuit protection resistance (r 1 ) 3.0k ? load resistance (r 2 ) 3.1k ? input rise and fall times 1ns/v input pulse voltages 0 to v cc input and output timing ref. voltages v cc /2 output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc output transition timing reference voltage 0v 0.7v cc 0.3v cc ai05814 v cc out c l includes jig capacitance device under test c l r 1 r 2
m68af127b 10/23 table 5. capacitance note: 1. sampled only, not 100% tested. 2. at t a = 25c, f = 1mhz, v cc = 3.0v. table 6. dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e1 = v il , e2 = v ih , v in = v ih or v il . 3. e1 0.2v or e2 v cc ?0.2v, v in 0.2v or v in v cc ?0.2v. 4. output disabled. symbol parameter (1,2) test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 6pf c out output capacitance v out = 0v 8pf symbol parameter test condition min typ max unit i cc1 (1,2) supply current v cc = 5.5v , f = 1/t avav , i out = 0ma 55 7.5 20 ma 70 6.0 15 ma i cc2 (3) operating supply current v cc = 5.5v , f = 1mhz , i out = 0ma 2ma i li input leakage current 0v v in v cc ?1 1 a i lo (4) output leakage current 0v v out v cc ?1 1 a i sb standby supply current cmos v cc = 5.5v , e1 v cc ? 0.2v , e2 0.2v , f=0 2.5 15 a v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ?0.3 0.8 v v oh output high voltage i oh = ?1ma 2.4 v v ol output low voltage i ol = 2.1ma 0.4 v
11/23 m68af127b figure 9. address controlled, read mode ac waveforms note: e1 = low, e2 = high, g = low, w = high. figure 10. chip enable or output enable controlled, read mode ac waveforms note: write enable (w ) = high. ai05474 tavav tavqv taxqx a0-a16 dq0-dq7 valid data valid ai05476 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a16 e1 g dq0-dq7 valid e2
m68af127b 12/23 figure 11. chip enable controlled, standby mode ac waveforms ai05477 tpd i cc tpu i sb 50% e1 e2
13/23 m68af127b table 7. read and standby mode ac characteristics note: 1. test conditions assume transition timing reference level = 0.3v cc or 0.7v cc . 2. at any given temperature and voltage condition, t ghqz is less than t glqx and t ehqz is less than t elqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. symbol parameter m68af127b unit 55 70 t avav read cycle time min 55 70 ns t av qv address valid to output valid max 55 70 ns t axqx (1) data hold from address change min 5 5 ns t ehqz (2,3) chip enable high to output hi-z max 20 25 ns t elqv chip enable low to output valid max 55 70 ns t elqx (1) chip enable low to output transition min 5 5 ns t ghqz (2,3) output enable high to output hi-z max 20 25 ns t glqv output enable low to output valid max 25 35 ns t glqx (2) output enable low to output transition min 5 5 ns t pd chip enable or ub /lb high to power down max 55 70 ns t pu chip enable or ub /lb low to power up min 0 0 ns
m68af127b 14/23 figure 12. write enable controlled, write ac waveforms figure 13. chip enable controlled, write ac waveforms ai05478 tavav twhax tdvwh data input a0-a16 e1 w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx e2 telwh ai05479 tavav tehax tdveh a0-a16 e1 w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input e2 twleh
15/23 m68af127b table 8. write mode ac characteristics note: 1. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. 2. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. symbol parameter m68af127b unit 55 70 t avav write cycle time min 55 70 ns t av eh address valid to chip enable high min 45 60 ns t avel address valid to chip enable low min 0 0 ns t av wh address valid to write enable high min 45 60 ns t avwl address valid to write enable low min 0 0 ns t dveh input valid to chip enable high min 25 30 ns t dvwh input valid to write enable high min 25 30 ns t ehax chip enable high to address transition min 0 0 ns t ehdx chip enable high to input transition min 0 0 ns t eleh chip enable low to chip enable high min 45 60 ns t elwh chip enable low to write enable high min 45 60 ns t whax write enable high to address transition min 0 0 ns t whdx write enable high to input transition min 0 0 ns t whqx (1) write enable high to output transition min 5 5 ns t wleh write enable low to chip enable high min 45 60 ns t wlqz (1,2) write enable low to output hi-z max 20 20 ns t wlwh write enable low to write enable high min 45 60 ns
m68af127b 16/23 figure 14. e1 controlled, low v cc data retention ac waveforms figure 15. e2 controlled, low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. all other inputs at v ih v cc ?0.2v or v il 0.2v. 2. tested initially and after any design or process that may affect these parameters. t avav is read cycle time. 3. no input may exceed v cc +0.2v. ai07204 data retention mode tr 5.5v tcdr v cc 4.5v v dr > 2.0v e1 e1 v dr ? 0.2v ai07205b data retention mode tr 5.5v tcdr v cc 4.5v v dr > 2.0v e2 e2 0.2v symbol parameter test condition min max unit i ccdr (1) supply current (data retention) v cc = 2.0v, e1 v cc ?0.2v or e2 0.2v, f = 0 4.5 a t cdr (1,2) chip deselected to data retention time 0 ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e1 v cc ?0.2v or e2 0.2v, f = 0 2.0 v
17/23 m68af127b package mechanical figure 16. so32 - 32 lead plastic small outline, package outline note: drawing is not to scale. table 10. so32 - 32 lead plastic small outline, package mechanical data symbol millimeters inches typ min max typ min max b 0.36 0.51 0.014 0.020 a 3.00 0.118 a1 0.10 0.004 a2 2.57 2.82 0.101 0.111 c 0.15 0.30 0.006 0.012 cp 0.10 0.004 d 20.14 20.75 0.793 0.817 e 11.18 11.43 0.440 0.450 e1 13.87 14.38 0.546 0.566 e 1.27 ? ? 0.050 ? ? l 0.58 0.99 0.023 0.039 l1 1.19 1.60 0.047 0.063 n32 32 e 16 e a2 d c e1 a 17 32 1 b so-c cp a1 l l1
m68af127b 18/23 figure 17. pdip32 - 32 pin plastic dip, 600 mils width, package outline note: drawing is not to scale. table 11. pdip32 - 32 pin plastic dip, 600 mils width, package mechanical data symbol millimeters inches typ min max typ min max a 4.83 0.190 a1 0.38 0.015 a2 3.81 0.150 b 0.41 0.53 0.016 0.021 b1 1.14 1.65 0.045 0.065 c 0.23 0.38 0.009 0.015 d 41.78 42.29 1.645 1.665 ea 15.24 ? ? 0.600 ? ? e 2.54 ? ? 0.100 ? ? e 15.24 15.88 0.600 0.625 e1 13.46 13.97 0.530 0.550 l 3.05 3.56 0.120 0.140 s 1.65 2.21 0.065 0.087 0 15 0 15 n32 32 pdip-c a2 a1 a l b1 b e d s e1 e n 1 c ea d2
19/23 m68af127b figure 18. tsop32 - 32-lead thin small outline package, 8x13.4mm, package outline note: drawing is not to scale. table 12. tsop32 - 32-lead thin small outline package, 8x13.4mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.91 1.05 0.0358 0.0413 b 0.22 0.0087 c 0.10 0.21 0.0039 0.0083 cp 0.10 0.0039 d 13.40 ? ? 0.5276 ? ? d1 11.80 ? ? 0.4646 ? ? e 8.00 ? ? 0.3150 ? ? e 0.50 ? ? 0.0197 ? ? l 0.40 0.60 0.0157 0.0236 0 5 0 5 n32 32 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1
m68af127b 20/23 figure 19. tsop32 - 32 lead plastic thin small outline, 8x20mm, package outline note: drawing is not to scale. table 13. tsop32 - 32 lead plastic thin small outline, 8x20mm, package mechanical data millimeters inches symbol typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 b 0.170 0.250 0.0067 0.0098 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d 19.800 20.200 0.7795 0.7953 d1 18.300 18.500 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? e 7.900 8.100 0.3110 0.3189 l 0.500 0.700 0.0197 0.0276 0 5 0 5 n32 32 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1
21/23 m68af127b part numbering table 14. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. example: m68af127 b l 55 mc 6 t device type m68 mode a = asynchronous operating voltage f = 4.5 to 5.5v array organization 127 = 1mbit (128k x8) option 1 b = 2 chip enable option 2 l = l-die m = m-die speed class 55 = 55ns 70 = 70ns package mc = so32 b = pdip32 nk = tsop32 8x13.4mm n = tsop32 8x20mm operative temperature 1 = 0 to 70c 6 = ?40 to 85c shipping t = tape & reel packing
m68af127b 22/23 revision history table 15. document revision history date version revision details august 2001 1.0 first issue. 18-oct-2001 2.0 so32 package mechanical and data added (figure 1, 3 and 16, table 10). 29-nov-2001 3.0 note removed from ordering information scheme. 06-mar-2002 4.0 document status changed to data sheet. 17-may-2002 5.0 document globally revised. 31-may-2002 6.0 pdip32 package added (figure 1, 4 and 17, table 11). chip enable low v cc data retention clarified (figure 14 and 15, table 9). 09-sep-2002 6.1 tsop32 8x13.4mm and tsop32 8x20mm packages added (figure 1, 5, 18 and 19, table 12, 13 and 14). commercial code clarified. 02-oct-2002 6.2 title and header layout modified. 09-oct-2002 6.3 datasheet number simplified. 16-apr-2003 6.4 label corrected on ?e2 controlled, low v cc data retention ac waveforms? figure. 08-aug-2003 6.5 tsop package connections modified (figure 5). test conditions for iccdr modified in table 9, low v cc data retention characteristics. 21-aug-2003 6.6 tsop package connections modified (figure 5). 24-sep-2004 7 document structure modified: ? chapter operation moved before chapter maximum rating. ? ac characteristics tables and waveforms moved to the dc/ac parameters section. t pu ad t pd updated in table 7.
23/23 m68af127b information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
about st products applications support buy news & events st worldwide contact us login search the site part number search search for part #: m68af example: *74*00* matching documents: 1 - 2 of 2 generic part number(s) orderable part number(s) status product page/ datasheet description m68af127b m68af127bm70b6u m68af127bm70mc6t m68af127bm70n6 m68af127bm70n6t nrnd nrnd nrnd nrnd 1 mbit (128k x8) 5.0v asynchronous sram memories | ram for flash subsystem | sram, low power asynchronous, 5v, m68af m68af511a m68af511am70mc1u m68af511am70mc6t m68af511am70mc6u m68af511am70nc6 m68af511am70nc6t obsolete obsolete obsolete obsolete obsolete 4 mbit (512k x8) 5.0v asynchronous sram memories | ram for flash subsystem | sram, low power asynchronous, 5v, m68af search time: 0.076s all rights reserved ? 2007 stmicroelectronics :: terms of use :: privacy policy pa g e 1 of 1 stmicroelectronics | part number search 27-au g -2007 mhtml:file://c:\te mp\sgst\m68af.mht
about st products applications support buy news & events st worldwide contact us login search the site part number search search for part #: m68af127bm70b6u example: *74*00* matching documents: 1 - 1 of 1 generic part number(s) orderable part number(s) status product page/ datasheet description m68af127b m68af127bm70b6u nrnd 1 mbit (128k x8) 5.0v asynchronous sram memories | ram for flash subsystem | sram, low power asynchronous, 5v, m68af search time: 0.073s all rights reserved ? 2007 stmicroelectronics :: terms of use :: privacy policy pa g e 1 of 1 stmicroelectronics | part number search 27-au g -2007 mhtml:file://c:\temp\s gst\m68af127bm70b6u.mht

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